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1 ? fn8133.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-352-6832 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. preliminary x55060 64k dual voltage monitor with integrated system battery sw itch and eeprom features ? dual voltage monitoring ? active high and active low reset outputs ? four standard reset threshold voltages (4.6/2.9, 4.6/2.6, 2.9/1.6, 2.6/1.6) ?user programmable thresholds ? lowline output ? zero delayed por ? reset signal valid to v cc = 1v ? system battery switch-over circuitry ? long battery life with low power consumption ?<50a max standby current, watchdog on ?<30a max standby current, watchdog off ? selectable watchdog timer ?(0.15s, 0.4s, 0.8s, off) ? 64kbits of eeprom ? built-in inadvertent write protection ?power-up/power-down protection circuitry ?protect none(0), or all of eeprom array with programmable block lock ? protection ?in circuit programmable rom mode ? minimize eeprom programming time ?64 byte page write mode ?self-timed write cycle ?5ms write cycle time (typical) ? 10mhz spi interface modes (0,0 & 1,1) ? 2.7v to 5.5v power supply operation ? available packages ? 20-lead tssop description this device combines power -on reset control, battery switch circuit, watchdog timer, supply voltage supervi- sion, secondary voltage supervision, block lock protect and serial eeprom in one package. this combination lowers system cost, reduces board space require- ments, and increases reliability. applying power to the device activates the power-on reset circuit which holds reset /reset active for a period of time. this allows the power supply and oscilla- tor to stabilize before the processor can execute code. block diagram watchdog timer reset data register command decode, test & control logic si so sck cs v cc reset & watchdog timebase power-on, generation v cc monitor + - reset reset low voltage status register protect logic eeprom array watchdog transition detector wp 512 x 128 x-decoder v trip1 logic v2 monitor + - v trip2 logic system switch reset /mr lowline v2fail v2mon v batt v out (v1mon) battery wdo batt-on v out v out data sheet march 28, 2005
2 fn8133.0 march 28, 2005 a system battery switch circuit compares v cc (v1mon) with v batt input and connects v out to whichever is higher. this provides voltage to external sram or other circuits in the event of main power failure. the x55060 can drive 50ma from v cc and 250a from v batt . the device switches to v batt when v cc drops below the low v cc voltage threshold and v batt > v cc . the watchdog timer provides an independent protec- tion mechanism for microcontrollers. when the micro- controller fails to restart a timer within a selectable time out interval, the device activates the wdo signal. the user selects the interval from three preset values. once selected, the interval does not change, even after cycling the power. the device?s low v cc detection circuitry protects the user?s system from low vo ltage conditions, resetting the system when v cc (v1mon) falls below the minimum v cc trip point (v trip1 ). reset /reset is asserted until v cc returns to proper operating level and stabilizes. a second voltage monitor circuit tracks the unregulated supply or monitors a second power supply voltage to provide a power fail warni ng. intersil?s unique circuits allow the threshold for either voltage monitor to be reprogrammed to meet special needs or to fine-tune the threshold for applications requiring higher precision. ordering in formation x55060 pin configuration suffix vtrip1 vtrip2 temp range v20-4.5a 4.6 2.6 0c to 70c v20i-4.5a -40c to 85c v20-4.5 4.6 2.9 0c to 70c v20i-4.5 -40c to 85c v20-2.7a 2.9 1.65 0c to 70c v20i-2.7a -40c to 85c v20-2.7 2.6 1.65 0c to 70c v20i-2.7 -40c to 85c 20-pin tssop cs /wdi so nc 1 2 3 4 reset /mr v cc (v1mon) batt-on v out 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 reset lowline v2fail v2mon wp nc vss v batt sck nc nc si wdo x55060
3 fn8133.0 march 28, 2005 pin description pin name function 1cs /wdi chip select input. cs high, deselects the device and the so output pin is at a high impedance state. unless a nonvolatile write cycle is underway, the device will be in the standby power mode. cs low enables the device, placing it in the active power mode. prior to the start of any opera- tion after power-up, a high to low transition on cs is required. watchdog input. a high to low transition on the wdi pin restarts the watchdog timer. the absence of a high to low transition within the watchdog time out period results in reset /reset going active. 2 nc no internal connections 3so serial output. so is a push/pull serial data output pin. a read cycle shifts data out on this pin. the falling edge of the serial clock (sck) clocks the data out. 4 reset reset output . reset is an active high, open drain output which is the inverse of the reset output. 5lowline low v cc detect . this open drain output signal goes low when v cc < v trip1 and immediately goes high when v cc > v trip1 . this pin goes low 250ns before reset pin. 6v2fail v2 voltage fail output. this open drain output goes low when v2mon is less than v trip2 and goes high when v2mon exceeds v trip2 . there is no power-up reset delay circuitry on this pin. 7v2mon v2 voltage monitor input. when the v2mon input is less than the v trip2 voltage, v2fail goes low. this input can monitor an unregulated power s upply with an external resistor divider or can monitor a second power supply with no external components. connect v2mon to v ss or v cc when not used. 8wp write protect. the wp pin works in conjunction with a nonvolatile wpen bit to ?lock? the setting of the watchdog timer control and the memory write protect bits. 9 nc no internal connections 10 v ss ground 11 si serial input. si is a serial data input pin. input all opcodes, byte addresses, and memory data on this pin. the rising edge of the serial clock (sck) latches the input data. send all opcodes (table 1), addresses and data msb first. 12 nc no internal connections 13 nc no internal connections 14 sck serial clock. the serial clock controls the serial bus timing for data input and output. the rising edge of sck latches in the opcode, address, or data bits present on the si pin. the falling edge of sck changes the data output on the so pin. 15 v batt battery supply voltage. this input provides a backup supply in the event of a failure of the pri- mary v cc voltage. the v batt voltage typically provides the supply voltage necessary to maintain the contents of sram and also powers the inte rnal logic to ?stay awake.? if unused connect v batt to ground. x55060
4 fn8133.0 march 28, 2005 principles of operation power-on reset application of power to the x55060 activates a power- on reset circuit. this circuit goes active at about 1v and pulls the reset /reset pin active. this signal prevents the system microprocessor from starting to operate with insufficient volt age or prior to stabilization of the oscillator. when v cc exceeds the device v trip1 value for 150ms (nominal) the circuit releases reset /reset, allowing the proc essor to begin exe- cuting code. low v cc (v1mon) voltage monitoring during operation, the x55060 monitors the v cc level and asserts reset /reset if supply voltage falls below a preset minimum v trip1 . during this time the communication to the dev ice is interrupted. the reset /reset signal also pr events the microproces- sor from operating in a power fail or brownout condi- tion. the reset signal remains active until the voltage drops below 1v. these also remain active until v cc returns and exceeds v trip1 for t purst . low v2mon voltage monitoring the x55060 also monitors a second voltage level and asserts v2fail if the voltage falls below a preset mini- mum v trip2 . the v2fail signal is either ored with reset to prevent the microprocessor from operating in a power fail or brownout condition or used to inter- rupt the microprocessor with notification of an impend- ing power failure. v2fail remains active until v2mon returns and exceeds v trip2 . the v2mon voltage sensor is powered by v out . if v cc and v batt go away (i.e. v out goes away), then v2mon cannot be monitored. 16 v out output voltage. v out = v cc if v cc > v trip1 . if v cc < v trip1 , then, v out = v cc if v cc > v batt +0.03 v out = v batt if v cc < v batt -0.03 note: there is hysteresis around v batt 0.03v point to avoid oscillation at or near the switchover voltage. a capacitance of 0.1f must be connected to vout to ensure stability. 17 batt-on battery on. this open drain output goes high when the v out switches to v batt and goes low when v out switches to v cc . it is used to drive an external pnp pass transistor when v cc = v out and current requirements are greater than 50ma. the purpose of this output is to drive an external transistor to get higher operating currents when the v cc supply is fully functional. in the event of a v cc failure, the battery voltage is applied to the v out pin and the external transistor is turned off. in this ?backup condition,? the battery only needs to supply enough voltage and current to keep sram devices from losing their data-there is no communication at this time. 18 reset /mr output/manual reset input . this is an input/output pin. reset output . this is an active low, open drain output which goes active whenever v cc falls below the minimum v cc sense level. when reset is active communication to the device is inter- rupted. reset remains active until v cc rises above the minimum v cc sense level for 150ms. reset also goes active on power-up and remains active for 150ms after the power supply stabilizes. mr input . this is an active low debounced input. when mr is active, the reset/reset pins are asserted. when mr is released, the reset/reset remains asserted for t purst , and then re- leased. 19 wdo watchdog output. wdo is an active low, open drain output which goes active whenever the watchdog timer goes active. wdo remains active for 150ms, then returns to the inactive state. 20 v cc (v1mon) supply voltage/v1 voltage monitor input. when the v1mon input is less than the vtrip1 voltage, reset and reset go active. pin description (continued) pin name function x55060
5 fn8133.0 march 28, 2005 figure 1. two uses of dual voltage monitoring watchdog timer the watchdog timer circuit monitors the microproces- sor activity by monitoring the cs/ wdi pin. the micro- processor must toggle the cs/ wdi pin high to low periodically prior to the expiration of the watchdog time out period to prevent the wdo signal going active. the state of two nonvolatile control bits in the status register determines the watchdog timer period. the microprocessor can change these watchdog bits by writing to the status register. the factory default set- ting disables the watchdog timer. the watchdog timer oscillato r stops when in battery backup mode. it re-starts when v cc returns. system battery switch as long as v cc exceeds the low voltage detect thresh- old v trip1 , v out is connected to v cc through a 5 ? (typical) switch. when the v cc has fallen below v trip , then v cc is applied to v out if v cc is equal to or greater than v batt + 0.03v. when v cc drops to less than v batt - 0.03v, then v out is connected to v batt through an 80 ? (typical) switch. v out typically sup- plies the system static ram voltage, so the switchover circuit operates to protect the contents of the static ram during a power failure. typically, when v cc has failed, the srams go into a lower power state and draw much less current than in their active mode. when v cc returns, v out switches back to v cc when v cc exceeds v batt + 0.03v. there is a 60mv hyster- esis around this battery switch threshold to prevent oscillations between supplies. while v cc is connected to v out the batt-on pin is pulled low. the signal can drive an external pnp transistor to provide additional current to the external circuits during normal operation. operation the device is in normal operation with v cc as long as v cc > v trip1 . it switches to the battery backup mode when v cc goes away. x55060 x55060 v out 5v reg 5v reg 3.3v reg v cc v cc reset reset v2mon v2mon v2fail v2fail system reset unregulated supply system reset system interrupt r1 r2 unregulated supply r1 and r2 selected so v2 = v2mon threshold when unregulated supply reaches 6v. notice: no external components required to monitor two voltages. v out v2 condition mode of operation v cc > v trip1 normal operation. v cc > v trip1 & v batt = 0 normal operation without battery back up capability. 0 v cc v trip1 and v cc < v batt battery backup mode; reset signal is asserted. no communica- tion to the device is allowed. x55060
6 fn8133.0 march 28, 2005 manual reset by connecting a push-button from mr to ground or driven by logic, the designe r adds manual system reset capability. the reset/reset pins are asserted when the push-button is closed and remain asserted for t purst after the push-button is released. this pin is debounced so a push-button connected directly to the device will have both clean falling and rising edges on mr . v cc (v1mon), v2mon threshold programming procedure the x55060 is shipped with standard v cc (v1mon) and v2mon threshold (v trip1 , v trip2 ) voltages. these values will not change over normal operating and storage conditions. however, in applications where the standard thresholds are no t exactly right, or if higher precision is needed in the threshold value, the x55060 trip points may be adjusted. the procedure is described below, and uses the application of a high voltage con- trol signal. setting the v trip voltage this procedure is used to set the v trip1 or v trip2 to a lower or higher voltage value. it is necessary to reset the trip point before setting the new value to a lower level. to set the new voltage, apply the desired v trip1 threshold voltage to the v cc pin or the v trip2 voltage to the v2mon pin (when setting v trip2 , v cc should be same voltage as v2mon). next, tie the wp pin to the programming voltage v p . then, send the wren command and write to address 01h or to address 0bh to program v trip1 or v trip2 , respectively (followed by data byte 00h). the cs going high after a valid write operation initiates the programming sequence. bring wp low to complete the operation. to check if the v tripx has been set, apply a voltage higher than v tripx to the vxmon (x = 1, 2) pin. dec- rement vxmon in small steps and observe where the output switches. the voltage at which this occurs is the v tripx (actual). c ase a if the v tripx (actual) is lower than the v tripx (desired), then add the difference between v tripx (desired) and v tripx (actual) to the original v tripx (desired). this is your new v tripx voltage that should be applied to vxmon and the whole sequence repeated again (see fig 6). c ase b if the v tripx (actual) is higher than the v tripx (desired), perform the reset sequence as described in the next section. the new v tripx voltage to be applied to vxmon will now be: v tripx (desired) - (v tripx (desired) - v tripx (actual)). note: this operation will not al ter the contents of the eeprom. figure 2. example system connection v cc 5v reg + unregulated supply address decode enable sram addr v cc nmi reset spi c v batt v2mon v ss batt-on v out v2fail reset cs , sck si, so v out pnp transistor or p-channel fet x55060
7 fn8133.0 march 28, 2005 resetting the v trip voltage to reset v trip1 , apply greater than 3v to v cc (v1mon). to reset v trip2 , apply greater than 3v to both v cc and v2mon. next, tie the wp pin to the programming voltage v p . then send the wren command and write to address 03h or 0dh to reset the v trip1 or v trip2 respectively (followed by data byte 00h). the cs going low to high after a valid write operation initiates the programming sequence. bring wp low to complete the operation. note: this operation does not change the contents of the eeprom array. figure 3. set v tripx level sequence figure 4. reset v tripx level sequence 01234567 0123456 cs sck si 16 bits 78910 2021 22 23 wp v p = 10-15v 06h wren 02h write 00h data 0001h/000bh address addr 01h: set v trip1 addr 0bh: set v trip2 01234567 0123456 cs sck si 16 bits 78910 2021 22 23 wp v p = 10-15v 06h wren 02h write 00h data 0003h/000dh address addr 03h: reset v trip1 addr 0dh: reset v trip2 x55060
8 fn8133.0 march 28, 2005 figure 5. sample v trip circuit figure 6. v trip programming sequence flow chart cs v cc v p adjust run v trip adj. so wp v ss reset sck si x55060 4.7k reset so cs si sck c v tripx programming apply v cc and voltage decrease v x actual v tripx - desired v tripx done set higher v tripx sequence error < mde ? | error | < | mde | yes no error > mde + > desired v tripx to v x desired present value? v tripx < execute no yes execute v tripx reset sequence set v x = desired v tripx new v x applied = old v x applied + | error | new v x applied = old v x applied - | error | execute reset v tripx sequence output switches? note: x = 1, 2 let: mde = maximum desired error vx = vxmon mde + desired value mde ? acceptable error range error = actual - desired x55060
9 fn8133.0 march 28, 2005 spi serial memory the memory portion of the device is a cmos serial eeprom array with intersil?s block lock protection. the array is internally organized as x 8. the device features a serial peripheral interface (spi) and software proto- col allowing operation on a simple four-wire bus. the device utilizes intersil?s proprietary direct write ? cell, providing a minimu m endurance of 100,000 cycles and a minimum data retention of 100 years. the device is designed to interface directly with the synchronous serial peripheral interface (spi) of many popular microcontroller familie s. it contains an 8-bit instruction register that is accessed via the si input, with data being clocked in on the rising edge of sck. cs must be low during the entire operation. all instructions (table 1), addresses and data are transferred msb first. data input on the si line is latched on the first rising edge of sck after cs goes low. data is outp ut on the so line by the falling edge of sck. sck is static, allowing the user to stop the clock and then start it ag ain to resume operations where left off. write enable latch the device contains a write enable latch. this latch must be set before a write operation is initiated. the wren instruction sets the latch and the wrdi instruc- tion resets the latch (figure 9). this latch is automati- cally reset upon a power-up condition and after the completion of a valid write cycle. status register the rdsr instruction provides access to the status register. the status regist er may be read at any time, even during a write c ycle. the status register is formatted as follows: the write-in-progress (wip) bi t is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. the wip bit is read using the rdsr instruction. when set to a ?1?, a non- volatile write operation is in progress. when set to a ?0?, no write is in progress. table 1. instruction set note: *instructions are shown msb in leftmost pos ition. instructions are transferred msb first. table 2. block protect matrix 76543210 wpen wd1 wd0 pup bl1 bl0 wel wip instruction name instru ction format* operation wren 0000 0110 set the write enable latch (enable write operations) wrdi 0000 0100 reset the write enable latch rsdr 0000 0101 read status register wrsr 0000 0001 write status register (watchdog, block lock, wpen) read 0000 0011 read data from memory array beginning at selected address write 0000 0010 write data to memory array beginning at selected address wren cmd status register device pin block block status register wel wpen wp protected block unprotected block wpen, bl0, bl1, pup, wd0, wd1 0 x x protected protected protected 1 1 0 protected writable protected 1 0 x protected writable writable 1 x 1 protected writable writable x55060
10 fn8133.0 march 28, 2005 the write enable latch (wel) bit indicates the status of the write enable latch. when wel = 1, the latch is set high and when wel = 0 the latch is reset low. the wel bit is a volatile, read only bit. it can be set by the wren instruction and can be reset by the wrds instruction. the block lock bits, bl0 and bl1, set the level of block lock protection. these nonvolatile bits are pro- grammed using the wrsr instruction and allow the user to protect one quarter, one half, all or none of the eeprom array. any portion of the array that is block lock protected can be read but not written. it will remain protected until the bl bits are altered to disable block lock protection of that portion of memory. the power-on reset time (t purst ) bit, pup sets the initial power or reset time. there are two standard settings. the watchdog timer bits, wd0 and wd1, select the watchdog time-out period. th ese nonvolatile bits are programmed with the wrsr instruction. the nonvolatile wpen bit is programmed using the wrsr instruction. this bi t works in conjunction with the wp pin to provide an in-circuit programmable rom function (table 2). wp tied to v ss and wpen bit programmed high disables all status register write operations. note 1. watchdog timer is shipped disabled. 2. the t purst time is set to 150ms at the factory. in circuit programmable rom mode this mechanism protects the block lock and watchdog bits from inadvertent corruption. in the locked state (programmable rom mode) the wp pin is low and the nonvolatile bit wpen is ?1?. this mode disables nonvolat ile writes to the device?s status register. setting the wp pin low while wpen is a ?1? while an internal write cycle to the status register is in progress will not stop this write oper ation, but the operation dis- ables subsequent write attempts to the status register. figure 7. read eepr om array sequence status register bits array addresses protected bl1 bl0 x55060 0 0 none (factory setting) 0 1 none 1 0 none 1 1 0000h?1fffh (all) pup time 0 150 milliseconds (factory settings) 1 800 milliseconds status register bits watchdog time out (typical) wd1 wd0 0 0 800 milliseconds 0 1 400 milliseconds 1 0 150 milliseconds 1 1 disabled (factory setting) 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 7 654321 0 data out cs sck si so msb high impedance instruction 16 bit address 15 14 13 3 2 1 0 x55060
11 fn8133.0 march 28, 2005 when wp is high, all function s, including nonvolatile writes to the status register operate normally. setting the wpen bit in the status register to ?0? blocks the wp pin function, allowing writes to the status register when wp is high or low. setting the wpen bit to ?1? while the wp pin is low activates the programma- ble rom mode, thus requiring a change in the wp pin prior to subsequent status register changes. this allows manufacturing to in stall the device in a system with wp pin grounded and still be able to program the status register. manufactur ing can then load configu- ration data, manufacturing time and other parameters into the eeprom, then set the portion of memory to be protected by setting the block lock bits, and finally set the ?otp mode? by setting the wpen bit. data changes to protected areas of the device now require a hardware change. read sequence when reading from the eeprom memory array, cs is first pulled low to select the device. the 8-bit read instruction is transmitted to the device, followed by the 16-bit address. after the read opcode and address are sent, the data stored in the memory at the selected address is shifted out on the so line. the data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. the address is automatically incremented to the next higher address after each byte of data is shifted out. the read operation is terminated by taking cs high. refer to the read eeprom array sequence (figure 7). to read the status register, the cs line is first pulled low to select the device followed by the 8-bit rdsr instruction. after the rdsr opcode is sent, the contents of the status register are shifted out on the so line. refer to the read status register sequence (figure 8). refer to the serial output timing on page 18. write sequence prior to any attempt to writ e data into th e device, the ?write enable? latch (wel) must first be set by issu- ing the wren instru ction (figure 9). cs is first taken low, then the wren instruction is clocked into the device. after all eight bits of the instruction are trans- mitted, cs must then be taken high. if the user con- tinues the write operation without taking cs high after issuing the wren instruction, the write opera- tion will be ignored. to write data to the eepro m memory array, the user then issues the write instruction followed by the 16 bit address and then the data to be written. any unused address bits are specified to be ?0?s?. the write operation minimally takes 32 clocks. cs must go low and remain low for the duration of the opera- tion. if the address counter reaches the end of a page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that may have been previously written. for the page write operation (byte or page write) to be completed, cs can only be brought high after bit 0 of the last data byte to be written is clocked in. if it is brought high at any other time, the write operation will not be completed (figure 10). to write to the status regi ster, the wrsr instruction is followed by the data to be written (figure 11). while the write is in progress following a status regis- ter or eeprom sequence, the status register may be read to check the wip bit. during this time the wip bit will be high. refer to se rial input ti ming on page 17. operational notes the device powers-up in the following state: ? the device is in the low power standby state. ? a high to low transition on cs is required to enter an active state and re ceive an instruction. ? so pin is high impedance. ? the write enable latch is reset. ? reset signal is active for t purst . data protection the following circuitry has been included to prevent inadverten t writes: ? a wren instruction must be issued to set the write enable latch. ? a valid write command and address must be sent to the device. ?cs must come high after a mu ltiple of 8 data bits in order to start a nonvolatile write cycle. x55060
12 fn8133.0 march 28, 2005 figure 8. read status register sequence figure 9. write enable latch sequence 01234567891011121314 76543210 data out cs sck si so msb high impedance instruction 01234567 cs si sck high impedance so x55060
13 fn8133.0 march 28, 2005 figure 10. write sequence figure 11. status register write sequence symbol table 32 33 34 35 36 37 38 39 sck si cs 012345678910 sck si instruction 16 bit address data byte 1 76543210 cs 40 41 42 43 44 45 46 47 data byte 2 76543210 data byte 3 76543210 data byte n 15 14 13 3 2 1 0 20 21 22 23 24 25 26 27 28 29 30 31 654 321 0 0123456789 cs sck si so high impedance instruction data byte 765432 10 10 11 12 13 14 15 waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance x55060
14 fn8133.0 march 28, 2005 absolute maximum ratings temperature under bias ................... -65c to +135c storage temperature ............ ............ -65c to +150c voltage on any pin with respect to v ss ...................................... -1.0v to +7v d.c. output current (all output pins except v out )............................. 5ma d.c. output current v out .................................. 50ma lead temperature (soldering, 10 seconds)........ 300c comment stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0c 70c industrial -40c +85c d.c. operating characteristics (over recommended operating conditio ns unless other wise specified. (v cc = 2.7v to 5.5v)) symbol parameter limits unit test conditions min. typ. (5) max. i cc1 (1) v cc supply current (active) (excludes i out ) read memory array (excludes i out ) write nonvolatile memory 1.5 3.0 ma sck = v cc x 0.1/v cc x 0.9 @ 10mhz i cc2 (2) v cc supply current (passive) (excludes i out ) wdt on, 5v (excludes i out ) wdt on, 2.7v (excludes i out ) wdt off, 5v 50.0 40.0 30.0 90.0 60.0 50.0 a cs = v cc , any input = v ss or v cc , v out , reset, reset , lowline = open i cc3 (1) v cc current (batte ry backup mode) (excludes i out ) 1av cc = 2v, v batt = 2.8v, v out , reset = open i batt1 (3)(7 ) v batt current (excludes i out )1av out = v bt i batt2 (7) v batt current (excludes i out ) (battery backup mode) 0.4 1.0 a v out = v batt , v batt =2.8v v out , reset = open v out1 (7) output voltage (v cc > v batt + 0.03v or v cc > v trip1 ) v cc - 0.05 v cc - 0.5 v cc -0.02 v cc -0.2 v v i out = -5ma i out = -50ma v out2 (7) output voltage (v cc < v batt -0.03v and v cc < v trip1 ) {battery backup} v batt - 0.2 v v i out = -250a v olb output (batt-on) low voltage 0.4 v i ol = 3.0ma (5v) i ol = 1.0ma (3v) v bsh battery switch hysteresis (v cc < v trip1 ) 30 -30 mv mv power-up power-down reset /reset/lowline /wdo v trip1 (6) v cc reset trip point voltage 4.5 4.62 4.75 v -4.5a and -4.5 versions 2.85 3.0 v -2.7a version 2.55 2.75 v -2.7 version v olr output (reset , reset, lowline , wdo ) low voltage 0.4 v i ol = 3.0ma (5v) i ol = 1.0ma (3v) x55060
15 fn8133.0 march 28, 2005 notes: (1) the device enters the active state after any start, and rema ins active until 9 clock cycles later if the device select bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or t wc after a stop ending a write operation. (2) the device goes into standby: 200ns after any stop, except those that initiate a high voltage write cycle; t wc after a stop that initiates a high voltage cycle; or 9 clock cycles afte r any start that is not followed by the corre ct device select bits in the slave addre ss byte. (3) negative number indicate charging current, positive numbers indicate discharge current. (4) v il min. and v ih max. are for reference only and are not tested. (5) v cc = 5v at 25c. (6) v trip1 and v trip2 are programmable. see page 22 and 23 for programming sp ecifications and pages 6, 7 and 8 for programming pro- cedure. for custom programm ed levels, contact factory. (7) based on characterization data. capacitance t a = +25c, f = 1mhz, v cc = 5v note: (1) this parameter is periodically sampled and not 100% tested. second supply monitor v trip2 (6) v2mon reset trip point voltage 2.85 3.0 v -4.5 version 2.55 2.7 v -4.5a version 1.6 1.7 v -2.7a and -2.7 version v olx output (v2fail ) low voltage 0.4 v i ol = 3.0ma (5v) i ol = 1.0ma (3v) spi interface v ilx (4) input (cs , si, sck, wp ) low voltage -0.5 v cc x 0.3 v v ihx (4) input (cs , si, sck, wp ) high voltage v cc x 0.7 v cc + 0.5 v i lix input leakage current (cs , si, sck,wp ) 10 a v ols output (so) low voltage 0.4 v i ol = 3.0ma (5v) i ol = 1.0ma (3v) v ohs output (so) high voltage v out - 0.8 v i oh = -1.0ma (5v) symbol test max. unit conditions c out (1) output capacitance (so, reset , v2fail , reset, lowline , batt-on,wdo )8 pfv out = 0v c in (1) input capacitance (sck, si, cs , wp )6pfv in = 0v d.c. operating characteristics (continued) (over recommended operating conditio ns unless other wise specified. (v cc = 2.7v to 5.5v)) symbol parameter limits unit test conditions min. typ. (5) max. x55060
16 fn8133.0 march 28, 2005 equivalent a.c. load circuit at 5v v cc a.c. test conditions a.c. characteristics (over recommended operating condit ions, unless otherwise specified) serial input timing v out so 30pf reset /reset 2.06k ? 3.03k ? v out 1.53k ? 30pf batt-on/lowline / v2fail , wdo input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x0.5 symbol parameter v cc = 2.7-5.5v unit min. max. f sck clock frequency 10 mhz t cyc cycle time 100 ns t lead cs lead time 50 ns t lag cs lag time 200 ns t wh clock high time 40 ns t wl clock low time 40 ns t su data setup time 10 ns t h data hold time 10 ns t ri (3) input rise time 20 ns t fi (3) input fall time 20 ns t cs cs deselect time 50 ns t wc (4) write cycle time 10 ms x55060
17 fn8133.0 march 28, 2005 serial input timing serial output timing notes: (3) this parameter is periodically sampled and not 100% tested. (4) t wc is the time from the rising edge of cs after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. symbol parameter 2.7-5.5v unit min. max. f sck clock frequency 10 mhz t dis output disable time 50 ns t v output valid from clock low 40 ns t ho output hold time 0 ns t ro (3) output rise time 25 ns t fo (3) output fall time 25 ns sck cs si so msb in t su t ri t lag t lead t h lsb in t cs t fi high impedance x55060
18 fn8133.0 march 28, 2005 serial output timing power-up and po wer-down timing sck cs so si msb out msb?1 out lsb out addr lsb in t cyc t v t ho t wl t wh t dis t lag t vb1 reset t vb2 t purst t purst t rpd v batt v cc v bat 0v v out v out v trip1 0v v out v cc reset batt-on x55060
19 fn8133.0 march 28, 2005 v cc to lowline timings v2mon to v2fail timings reset /reset/lowline output timing notes: (1) this parameter is not 100% tested. (2) this measurement is from 10% to 90% of the supply voltage. (3) v cc = 5v at 25c. (4) based on characterization data only. symbol parameter min. typ. (3) max. unit t purst reset/reset time-out period pup = 0 pup = 1 75 500 150 800 250 1200 ms t rpd (1) v trip1 to reset /reset (power-down only) v trip1 to lowline 10 20 s t rpd2 (1) v trip2 to v2fail 10 20 s t lr lowline to reset/reset delay (power-down only) 100 250 (4) 800 ns t f (2) v cc /v2mon fall time 1000 s t r (2) v cc /v2mon rise time 1000 s v rvalid reset valid v cc 1v t vb1 v batt + 0.03 v to batt-on (logical 0) 20 (4) s t vb2 v batt - 0.03 v to batt-on (logical 1) 20 (4) s v cc lowline v trip v batt v trip1 0v v oh v ol v trip1 0v t r t rpd t rpd t f v trip2 0v t r t rpd2 t rpd2 t f v2mon v2fail v out x55060
20 fn8133.0 march 28, 2005 cs /wdi vs. wdo timing reset /reset output timing notes: (1) v cc = 5v at 25c. (2) based on characterization data only. v trip set/reset conditions symbol parameter min. typ. (1) max. unit t wdo watchdog time out period, wd1 = 1, wd0 = 0 wd1 = 0, wd0 = 1 wd1 = 0, wd0 = 0 75 200 500 150 400 (2) 800 (2) 250 600 1200 ms ms ms t cst cs pulse width to reset the watchdog 400 ns t rst reset time out 75 150 250 ms cs /wdi t cst wdo t wdo t rst t wdo t rst sck cs * 0001h set v trip1 02h v cc /v2mon wp t thd t vph t vps v p v tripx t wc t vpo t pcs * 0003h set v trip2 06h * 000bh reset v trip1 * 000dh reset v trip2 si x = 1, 2 t tsu * all others reserved 0n 8 clocks x55060
21 fn8133.0 march 28, 2005 v trip1 , v trip2 programming specifications v cc = 2.7-5.5v; temperature = 25c parameter description min. max. unit t vps wp v tripx program voltage setup time 10 s t vph wp v tripx program voltage hold time 10 s t tsu v tripx level setup time 10 s t thd v tripx level hold (stable) time 10 ms t wc v tripx write cycle time 10 ms t vpo wp v tripx program voltage off time before next cycle 1 ms v p programming voltage 10 15 v v tran v tripx programed voltage range 2.5 5.0 v v tv v tripx program variation after programmi ng (0?75c). (programmed at 25c ac- cording to the procedure defined on pages 6, 7 and 8.) -25 +25 mv v tripx programming parameters are periodically sampled and are not 100% tested. x55060
22 fn8133.0 march 28, 2005 packaging information note: all dimensions in inches (in parentheses in millimeters) 20-lead plastic, tsso p, package type v see detail ?a? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 - 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) x55060
23 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8133.0 march 28, 2005 part mark information v20 = 20-lead tssop w x55060 x yyww date code part mark v trip1 range v trip2 range operating temperature range part number blank 4.5-4.75v 2.55-2.7v 0c-70c x55060v20-4.5a i -40c-85c x55060v20i-4.5a al 4.5-4.75v 2.85-3.0v 0c-70c x55060v20-4.5 am -40 c-85 c x55060v20i-4.5 f 2.85-3.0v 1.6-1.7v 0c-70c x55060v20-2.7a g-40 c-85 c x55060v20i-2.7a an 2.55-2.75v 1.6-1.7v 0c-70c x55060v20-2.7 ap -40 c-85 c x55060v20i-2.7 x55060

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